package NICE_CORE
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import firrtl.options.TargetDirAnnotation


object u_e203_nice_core_bitwise_8bit_zf_config_144k_wisenum extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_bitwise_8bit_zf_config_144k_wisenum()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_e203_nice_core_144k extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_144k()),
      TargetDirAnnotation("Verilog"))
  )
}


object u_e203_nice_core_bitwise_8bit_zf_config extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_bitwise_8bit_zf_config()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_e203_nice_core_bitwise_8bit_zf_config_144k extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_bitwise_8bit_zf_config_144k()),
      TargetDirAnnotation("Verilog"))
  )
}


object u_e203_nice_core_bitwise_8bit_zf extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_bitwise_8bit_zf()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_e203_nice_core extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_e203_nice_core_bitwise extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_bitwise()),
      TargetDirAnnotation("Verilog"))
  )
}
object u_e203_nice_core_bitwise_8bit extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new e203_nice_core_bitwise_8bit()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_EndianCnvt extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new EndianCnvt(128)),
      TargetDirAnnotation("Verilog"))
  )
  val temp_verilog = (new chisel3.stage.ChiselStage).emitVerilog(new EndianCnvt(128))
  println(temp_verilog)
}

object u_cim_mvm extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new cim_mvm),
      TargetDirAnnotation("Verilog"))
  )
  val temp_verilog = (new chisel3.stage.ChiselStage).emitVerilog(new cim_mvm)
  println(temp_verilog)
}

object u_cim_mvm_2 extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new cim_mvm_2(16)),
      TargetDirAnnotation("Verilog"))
  )
  //val temp_verilog = (new chisel3.stage.ChiselStage).emitVerilog(new cim_mvm)
  //println(temp_verilog)
}

